The Basic Concept Of Cic Filter Accounting Essay

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This paper presents a design and implementation of CIC based decimation filter for WCDMA Applications. This structure consists three stages. The comb decimation filter at the first stage operates at the input sampling rate and zero rotated sharpened second stage operates at lower sampling rate as compared to first section lesser than M1 decimation factor and compensation section is operates at lesser than M decimation factor. This multistage structure reduces the sampling rate at every stage of the CIC decimation filter. The sharpened second stage produces the wider passband droop and better stop band alias rejection. This wider passband droop will be compensated with the help of compensation section. This filter structure is designed with MATLAB Simulink environment and implemented with help of Virtex-V XC5VLX110T-3ff1136. Device utilization and simulation results are generated and tabulated. The developed structure improves the passband droop and stopband aliasing rejection.


CIC Filter, Filter sharpening, Zero rotation, Decimator, Compensation filter, MATLAB Simulink, Xilinx Virtex-V


WiMAX is a wireless data communication technology based around the IEEE 802.16 standard providing high speed data over a wide area. The WiMAX stands for World Wide Interoperability for Microwave Access and it is a technology for point to multipoint wireless networking. WiMAX technology expected to meet the needs of a large variety of users from those in developed nations wanting to install a new high speed data network very cheaply without the cost and time required to install a wide network, to those in rural areas needing fast access where wired solutions may not be viable because of distance and cost involved. Additionally it is being used for mobile applications, providing high speed data to users on the move. In this paper we are designing the decimation filter for WiMAX standard as per the specification mentioned in the table 1. The sampling rate reduction is required in WiMAX is 8, which is realized with multi stage realization techniques which improves the passband and stopband attenuation effectively and reduces the complexity, device utilization and power consumption as compared to single stage realization.

Table 1: WCDMA Specifications and Filter Design Parameters

Frequency range (GHz)

DL : 2.11 - 2.17

UL : 1.92 - 1.98 

Channel Spacing (MHz)


Data Rate

8.34 M chips/sec



Input sampling frequency Fs (MHz)


Pass band Edge (MHz)


Stop band Edge (MHz)


Pass band ripple (dB)


Stop band attenuation (dB)


The design and implementation of different decimation filter structure of CIC (Cascaded-integrator comb) filter with various techniques has been reported in the past few decades by many researchers [1-13]. In 1981, Eugene Hogenauer [1] proposed a class of digital filter for interpolation and decimation the advantages compared to other type of filters is it requires no multipliers and use limited storage hereby leading to more economical hardware implementations. They are designated as cascaded integrator-comb (CIC) filter, because structure consists of an equal number of integrator section operating at the high sampling rate and a comb section operating at the low sampling rate. J. F. Kaiser and R.W. Hamming [2] describes the filter sharpening technique based on the idea of amplitude change function (ACF) which is restricted to symmetric non-recursive (FIR) filters with piecewise constant passband and stopband.

A. Kwentus [3] designed and implemented a programmable CIC multirate decimation filter structure with filter sharpening techniques to improve the filters passband response. This allows the first stage CIC decimation filter to be followed by a fixed-coefficient second-stage filter rather than a programmable filter thereby achieving a significant hardware reduction over existing approaches. A low power fifth order decimation comb filter with programmable decimation ratio (16 and 8) and sampling rate (128 MHz and 44.8 GHz) for GSM and DECT application have been proposed by Y.Gao et al [4]. The low power consumption is achieved by following approaches. First the non-recursive architecture for comb filter is employed, second unnecessary computations eliminated with polyphase implementation of each stage and third each polyphase components implemented with data-broadcast structure.

Several schemes have been proposed by G. J. Dolecek and S.K.Mitra [5-7] to design CIC filters with improved magnitude response. The authors proposed a different structure that consists of a comb section and a sharpening comb section with the latter section operating at a lower rate than the high input rate for the realization of comb-decimation filter with a sharpened magnitude response. Applying sharpening with zero rotation to the decimation filter in the last stage provides very good results, saving in number of operations comparing to the case of sharpening of complete filter. M.Laddomada, [8 & 9] has presented the mathematical framework to optimize the decimation filters by introducing a class of sharpened modified comb filter aimed at increasing the rejection of quantization noise around the folding band and reducing the passband droops of the decimation filters.

The framework for zero rotation in the multistage CIC filter structure has been proposed by Marko Nikolic and MiroslavLutovac [12]. It was reported that the sharpening in the last stage of decimation filter enhances the performance and saving in number of operations comparing to the case of sharpening of complete filter. Shahana T.K et al [13] designed multistandard architecture as a solution for the future wireless transceivers to attain higher system capacities and data rates. An efficient reconfigurable implementation is a key to achieve low power consumption. They designed a dual mode RNS (Residue Number System) based decimation filter which can be programmed for WCDMA and WiMAX applications. Area utilized is increased by 24% to include WiMAX compared to Single Mode WCDMA Standards. Ioan lie et al [14] presented a synthesis and implementation of digital decimating filter for an Ultrasonic beam former, which uses delta sigma modulators to acquire the received ultrasonic signals. This design is implemented by a FPGA technology (Altera 10K series) and the simulation results are analyzed.

Ze Tao and Svante Signell [15] presented a delta sigma ADCs comprise the modulator and decimating filter for multistandard wireless applications namely. GSM, WCDMA, 802.11a, 802.11b, 802.11g and WiMAX. Shahana T.K et al [12], proposed a GUI based design tool for multistandard decimation filter for 6 wireless communication standards, consisting of GSM, WCDMA, 802.11a, 802.11b, 802.11g and WiMAX. The decimation is done in two or three stages to reduce the complexity and power dissipation. The main idea of this paper is to design and implement the multistage CIC decimation filter structure for WiMAX application by decimation factor 8, with the advantages presented earlier to obtain the structure which can operate at a lower sampling rate to achieve better performances than the original comb filter based structure.


Cascaded integrator comb [1] or Hogenauer filter, are multirate filters used for realizing large sample rate changes in digital systems. CIC filters are multiplierless structures, consisting of only adders and delay elements which is a great advantage when aiming at low power consumption. So the CIC filters are frequently used in digital down converter and digital up converters.

The CIC filter is a class of hardware efficient linear phase FIR digital filter consists of an equal number of stages of ideal integrator and comb filter pairs. The highly symmetric structure of this filter allows efficient implementation in hardware. However the disadvantage of a CIC filter is that is passband is not flat, which is undesirable in many applications. This problem can be overcome through the use of compensation filter. CIC filter achieve sampling rate decrease (decimation) without using multiplication. The CIC filter first performs the averaging operation then follows it with the decimation.

2.1 CIC filter for sample rate Conversion

The CIC filters are utilized in multirate systems for constructing digital up converter and down converter. The ability of comb filter to perform filtering without multiplication is very attractive to be applied to high rate signals; moreover CIC filters are convenient for large conversion factor, since the low pass bandwidth is very small. In multistage decimators with large conversion factor, the comb filter is the best solution for first decimation stage, whereas in interpolation, the comb filter is convenient for the last stage.

2.2 CIC filter for decimation

The basic concept of CIC filter is given in Figure 1 (a), which consists of factor of M down sampler and K-stage CIC filter. Applying third identity, the factor of M down sampler is moved and placed behind the integrator section and before the comb section as shown in Figure 1 (b). Finally the CIC decimator is implemented as a cascade of K integrator, factor of M down sampler and the cascade of K differentiator sections. The integrator portion operates at the input data rate, whereas the comb portion operates at M time's lower sampling rate.

(a) Cascade of CIC Filter and Down Sampler

(b) Cascade of Integrator Section, Down Sampler and Comb Section

(c) Implementation Structure of Single Stage CIC Filter

(d) Implementation Structure of CIC Filter with K Stages

Figure 1: Block Diagram representation of CIC Filter

The transfer function of the CIC filter in z-domain is given as [1].


Where, M is the decimation factor

In equation (1) the numerator (1-z-M) represents the transfer function of comb section and the denominator 1/ (1-z-1) indicates the transfer function of integrator section.

Figure 1(c) shows the first order CIC filter; here the clock divider circuit divides the oversampling clock signal by the oversampling ratio M after the integrator stage. The integrator operates at the input sampling frequency, while the differentiator operates at down sampled clock frequency fs /M. By operating differentiator at the lower sampling rate the power consumption is reduced.

A magnitude characteristic of the comb filter is improved by cascading [3] several identical comb filters which is shown in Figure 1 (d). The transfer function of multistage comb filter composed of identical single stage comb filter is given by,


Figure 2: Response of CIC filter with different K values

Figure 2 shows the frequency response of CIC filter for different stages, while increasing the K values passband droop decreases and stopband attenuation increases.


The structure proposed in this paper is shown in figure 4 which consists of two stages, the first stage H1L(z) is responsible for stopband alias rejection and the second stage {3[H1(zM1)]2K - 2[H1(zM1)]3K} is responsible for passband droop performance. By applying zeros rotation with sharpening technique in the second stage is expected to improve the stopband alias rejection compared to existing CIC filter structures. However it is expected to reduce the passband droop. This reduction can be minimized by cascading the sine compensator as a last stage.

Filter sharpening [2] is the technique to improve the passband droop and stopband attenuation using multiple realization of a low order basic filter having the form.


where, Hp(f) is a low order basic filter, n and m are non-negative integers represent the number of non-zero derivatives of Hnm(f) at points Hnm(f) = 0 and Hnm(f) = 1 respectively.

The Kaiser-Hamming sharpening technique applied to linear-phase FIR filters with group delay of D samples has the transfer function of H11(z), for n=1; m=1 can be written as


The term [3z-D - 2 Hp(z)] is responsible for passband droop reduction and Hp(z) is responsible for stopband rejection.

Generalized comb filter (GCF) with rotated zero [8, 9 & 12] has better distribution of nulls than multistage sharpened CIC filter in the stopband attenuation in the aliasing band. The 3rd order generalized comb filter (GCF3) [12] can be obtained from 3rd order CIC filter by rotating the zeros both sides with the angle . This can be denoted as GCF3 of (M, α) as modified comb filter of the third order used for decimation with factor M.

The transfer function of GCF3 (M, α) can be represented by,





From equation (14) and (15) the zero rotation function can be written in


Where, α is rotation angle,

is a filter quality parameter and ,

is the highest frequency of the input signal [8]

The generalized transfer function of two stage CIC filter can be written as


Decimation factor M=M1 * M2

The transfer function of two stage sharpened CIC filter can be written as


Applying zero rotation in the second stage of modified sharpened section of the filter, which distributes the nulls in the sharpened section. This improves the stopband alias rejection but slightly reduce the passband droop. This passband droop can be improved by introducing the sine compensator as third stages. The block diagram of the CIC filter with compensator is shown in figure 4.

The input of the second stage is obtained from the decimated output of the first stage. This is expected to reduce the computational complexity by M1 times. Then the sharpened zero rotation is applied to the second stage along with decimation factor M2. The rotated and decimated output obtained from the second stage is given to the compensator to improve the passband droop.

Generally sine compensation is found to be one of the methods to improve the passband performance of the filter. Consider the filter with transfer function given [6].


Here, A = ; B =

The compensation filter parameter 'b' depends on the value of K, not on the decimation factor M. For the given value of b and K, the value of decimation factors not expected to affect the worst case alias rejection.

The transfer function of the zero rotated CIC filter with compensator can be written as,


The developed CIC filter with compensator is realized and shown in figure 4. The first stage is comb decimator with decimation factor M1 which can be realized in either recursive or non-recursive scheme. As a result second stage (sharpened zero rotated) is moved to a lower rate which is M1 times lower than the input rate. The compensation filter plays an important role for compensation of the passband droop introduced by the second stage.

Figure 3: Modified Sharpened CIC Filter Structure

Figure 4: Proposed CIC Filter Structure


The recent advancement in the VLSI technology particularly in FPGA as made possible, the realization of advanced Digital Signal Processing algorithm in high frequency domain. With this development a single chip solution is possible for complex DSP based applications like, ADC, Decimation and Interpolation in the communication system.

A digital implementation couple with signal processing algorithms greatly enhances the system performance, reduces the cost and increase the reliability of the system. Low power DSP systems are implemented by changing the sampling clock for each subsystem depending on the real requirements. The sampling rate change results in aliasing; this necessitates the use of filters to overcome it. So in this section we discuss the implementation of sharpened CIC filter structure.

The initial model was designed and tested in Simulink. Simulink is a software package from Mathworks for modeling, simulating the dynamic systems. This Simulink model is used as the reference model for synthesis of the design in FPGA. To target the module for FPGA, we choose to use Xilinx System Generator, which provide a Simulink blockset that is then converted to VHDL for synthesis and implementation. This VHDL generation flow is shown in figure 5. The figure 7, 8 and 9 shows the model of the Basic CIC, Modified CIC and Proposed CIC Filter Implementation Structures respectively.

Each filter structure is designed in MATLAB Simulink environment using FDA Tool and tested the Decimation filter architecture with different input signal. The same will be implemented using Xilinx tool boxes, the VHDL code and Testbench for the designed Simulink model was generated using System Generator HDL Coder. This method is efficient and it takes less time to test and implement a design as compared to the task of writing HDL Code for individual component.

Figure 5: FPGA Synthesis Flow

Figure 6: Realization of CIC Filter Structure with K=1

Figure 7: Realization of Modified Sharpened CIC Filter Structure with K=1and L=2

Figure 8: Realization of Proposed CIC Filter Structure with K=1and L=2


The CIC filter with sharpening, zero rotation and compensation is developed and the frequency response for the decimation factor M = 16 with different stages are obtained. Various parameters considered for analysis is given in table 1.

The magnitude response for the decimation filter with and without compensator have been computed and shown in figure 9 for M=16 with K=2 and L=4. Figure 9 (a) shows the overall magnitude response of CIC filter with and without compensator for M1 = 4 and M2 = 4. It is clear from the figure that passband droop is improved and the stopband alias rejection is reduced compared to the structures reported earlier. The expanded portion of the passband droop and stopband alias rejection is shown in figure 9 (b) and 9 (c) respectively for clear understanding. Figure 10, 11 and 12 shows the basic CIC filter, modified sharpened CIC filter and the proposed CIC filter structure simulated output waveforms.

(a) Overall magnitude responses

(b) Passband zooms

(c) Detailed view of the magnitude response around the first null

Figure 9: Magnitude responses plots for M=8, M1=2, M2=4 with K=1 and L=2

Figure 10: Output waveform of Proposed CIC Filter Structure with K=1and L=2 using Wave scope

Figure 11: Output waveform of Proposed CIC Filter Structure with K=1and L=2 using Scope

Figure 12: Output waveform of Proposed CIC Filter Structure with K=1and L=2 using Scope

Table 2 shows the device utilization summary, passband, stopband performance of basic CIC, modified CIC and Proposed CIC structure. Compared to basic CIC and modified CIC filter structure, proposed CIC filter with and without compensator but the proposed structure gives 47 % improvement in passband droop performance and 8 % improvement in stopband attenuation.


The proposed CIC filter structure with and without compensator was designed and implemented with help of FPGA kit Virtex-V and simulation results are graphed and tabulated for a decimation factor of 16. The evaluation shows that improvement in the passband droop and stopband attenuation performance of the designed CIC filter as compared to existing filter structures. The implementation result shows the device utilization summary of the designed filter structure. This decimation filter is best suited for WCDMA and DSP related application. The same filter structure with decimation factor 8 is suited for WiMAX decimation filtering.

Table -2 Overall Comparison of Proposed CIC Performance with existing























in Watts







CIC [1]









Modified Sharpened CIC [5]












Proposed CIC without Compensator












Proposed CIC with Compensator












Passband Droop and Stopband Improvement in Percentage

47 %

8 %