engineering

The engineering essay below has been submitted to us by a student in order to help you with your studies.

Vhdl codes and syntaxes

Introduction

Assignment Overview:

The task is to use VHDL codes and syntaxes to design couples of blocks in the way that leads to a core of a RISC microprocessor. The main parts of this microprocessor such as ALU, Register File and Decoder had been dictated among the 2 Lab sections and for an outstanding period of time, designing blocks and connecting them together such that, the microprocessor become to the point which able to add, subtract and do some other arithmetic operations is expected. For testing and simulating the performance of microprocessor individually, bunch of data due to ID number are suggested for making a stream of Machine Instruction. Furthermore thinking and applying learnt techniques for achieving to a faster, simpler and practical microprocessor are considered.

Interfaced Software:

The software used for coding is Active HDL 8.2 which is provided by department. This is a Windows based integrated FPGA Design and support IEEE-language. This software also prepares pre-compiled FPGA vendor libraries and it has ability to generate automatic test-bench.

Design Stages And Prototypes:

According to Fig.2 designing the microprocessor and testing its performance divided into two major sections. In the first section the basic expected design of the microprocessor is defined as a goal. Regarding to this goal, the main blocks i.e. ALU, Register File (ROM), Decoder and Op-code validity check were coded in a structural manner. The 32 addresses of register file were introduced by individual initial values. In the next stage each of the critical parts checked separately by using test-benches. Finally Decoder and ROM were synchronized by Clock, which is imported in a split file. Another test-bench applied to micro, the place where all the blocks connecting to each other, in order to test whole of the system. When the initial results of overall design come out and simulation tool plots the waveform of the design, then some requirements are defined in order to improve the design for making its performance more valuable and feasible. This improvement would be discussed later on this report.

Challenging Parts

Design Attitudes

Designing the Part of RISC similar to what has been discussed previously would be a little non-sense and firm to implement on the hardware, without optimizing the codes and editing particular hazards. In other words specific attitudes are expected in order to achieve a valuable and meaningful design. The following table focus on these attitudes:

Properties: Description: Alternatives:

Coding structure As an engineering practice, the codes should be editable and feasible.

The code should be easy to follow, in order to improve or add more features to the micro. Constructing different blocks for different parts of Micro.

Divided the architectures into 3 types (i.e. simple, Structure and processing).

Using named-association instead of positional- association for a core of Micro.

Price and Manufacturing For the real hardware, using both the rising edge and falling edge would be very expensive and harsh to manufacture.

The architectures must be adaptive with FPGA implementation. Sending each instruction in only 1 clock (Pipe-lining).

Arrange the efficient time of reaching to the final answer.

Using more than 32 Registers.

Using r0 and r31 in whole of the progress.

Corrupting the generation of usual clock signal.

Operation Time Fastest operation time is considered.

As the simulation starts the clock signal should be generated simultaneously. Forget about the price and present the simulation with the basic structure.

Implement the Pipe-Lining technique.

Bypass the Hazards The garbage values in register files might cause some problems when you switch on the device.

If the reading and writing addresses are the same then the result may not be true.

Invent the wrong delay in the codes.

Using inappropriate Pipe-lining.

Utilize the VHDL syntaxes badly. Creating the separate test benches for ALU and ROM

Using an enable signal to activate the Register file.

Adding one or two op-codes more than suggested numbers of them.

Apply 2 Buffers in the ROM to make necessary delays.

Simulation The final test progress must be clear and easy to track.

Just important results would be investigated. Using the meaningful and correct signals and ports names.

The Ideas behind the design:

(NB: It is strongly recommended to follow this part with Appendix 2)

Entity 1st R-E 2nd R-E 3rd R-E 4th R-E

Add1

Add2

Add3 Buffered

Op-code Buffered

Machine-Ins

ALU-a

ALU-b

ALU-Result

Register

The most important idea is how to deal with a received machine instruction in the first few clock cycles. Just after the first rising edge, the first machine instruction is read. Then the machine instruction (B"000011_00100_00101_00000_00000000000") is identified by decoder, and register addresses and op-codes are gained. While address3 and op-codes stay in buffer1 and buffer3, the address1 and address2 are directed to register file instantaneously. The values of the buffers would be delayed for one clock cycle. Having feed the ROM, the op-code must be checked in this rising edge (second rising edge) to find out if valid or not. This checking is mandatory since we need to produce an Enable signal in order to avoid initial values which may cause some problems for ROM.

In the third rising edge, the valid operation code is raise to ALU and both the operands are ready for ALU. After one clock cycle the address 3 is accessible for ROM. While the ALU work on operands to give a result, decoder read the second instruction and sends the next reading addresses to ROM. Again the op-code is checked for its validity.

In the next clock the result which is produced by ALU would be stored in the register 0, which is directed by Address3.

The same procedures are carried out sequentially on the stream of machine instruction. With this method which is called Pipe-Lining each instruction is produce in one clock cycle. In simulation results (Appendix 2), the final result is gained without any hazards. The last Machine instruction is No-operation instruction which turn the system off, since its op-code is not valid for the micro. Table.2 gives the summery of the process for the first machine instruction.

Conclusion:

Likewise the other programmes, this design might have some problems in its prototype or coding strategies. However this could be upgraded by implementing other blocks of RISC or it can be changed to more advanced topology by adding Additional Hardware Control Unit, using Multi-core processor or performing Accessing Memory and so on. But as a first experience, it was pretty understandable.

Programming and blocks portrayal

ALU:

ALU is asked to response for a certain numbers of Op-codes and it can apply sets of arithmetic operations on two inputs and generate the results according to these Op-codes. Op-code: 3 stands for summation; Op-code: 11 stands for subtraction, and so on.

Register file (ROM):

Entity Architecture

alu SIMPLE

rom

valid

decode

clock

micro STRUCTURE

test PROCESSING

ROM acts as small memory inside a processor for holding the operands. Among the progress this block is frequently called in order to convert the words, which are held in registers, to integers and vice versa. Also this block is synchronized with a clock signal.

Decoding Block:

Machine-Instruction must be decoded somewhere to identify ROM and ALU which operation or operands are required in each clock cycle. Decoder extracts operation codes and three addresses from the instruction. Buffers are employed in this block to send Address3 and Op-code after one clock cycle.

Operation code validity control:

At first this block check the op-code, if op-code is valid, then it generates an enable signal. This enable signal keeps the ROM away from the garbage values which are previously stored in registers.

Testing The Whole Systems:

Name Block Propose

Buffer_1 Decoder Delay for Add3

Buffer_2 Test-bench Utilize for Counter

Buffer_3 Decoder Delay for Op-codes

Although each of the blocks has been tested separately, this block works on a simple programme to test the whole design. Test-bench is synchronized with a clock signal and in each clock-cycle sends one machine instruction. The aim is to calculating the result. The values stored in the first three registers should be subtracted from the total, the next three registers should be added to the total, the next three subtracted, and so on. For holding the machine instruction in the test-bench an array is used and a stream of them can be imported easily.

Clock Generator:

In order to avoid using the stimulator among the simulation, this block generate clock signal.

Micro:

Micro has a different architecture. For connecting the blocks together and Calling each of the above blocks, 6 structural operations (denoted by g1, g2 to g6) were used in the micro. This block also used commonly for simulation of whole system.


Request Removal

If you are the original writer of this essay and no longer wish to have the essay published on the UK Essays website then please click on the link below to request removal:

Request the removal of this essay


More from UK Essays