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### I. Introduction

Adder is an electronic device that mainly performs the addition operation on two binary inputs. It mainly add two binary number so it is called as binary adder. The operation of adding two binary number by the adder is shown in Table 1 where sum and carry occur represented by Σ and Co. From this it is clear that binary addition may create a carry to subsequent stages. There are two main types of adders

Some special types of adders are also doing for adding more than three bit and they are

Where in case of a Subtracter it mainly has two inputs similar to adder but it subtract one input from the other input which we supplied to the circuit of the subtracter. It also generated two outputs but here one is the subtraction between the input to the other and other is the borrow. It has also two types

* Half subtracter

* Full Subtracter

A

B

Carry (Co)

Sum (Σ)

0

0

0

0

0

1

0

1

1

0

0

1

1

1

1

0

When we add two numbers we start with the least significant column. This means that we have to add two bits. There will be also the possibility of carry in addition. The logic circuit of the half adder is shown in fig. 2 . It mainly consist of an EX-OR gate and a an AND gate. The output which is produced by the EX-OR gate is known as sum and the output of AND gate is known as the carry. AND gate produces a high output only when both inputs are high and EX-OR gate produces a high output if only one input is high. The truth table is generated by the output of AND gate in carry column and the outputtruth table of the EX-Or gate in the sum column.

Therefore from the truth table, the logical equations of Sum and Carry can be written as

Carry C= A.B

SUM S = A ⊕ B

Therefore the circuit is now formed is known as half adder because it cannot accept a CARRY- IN from previous additions. Due to this reason half adder circuit can be used only for the binary addition of lower most bit only. For the addition of higher order we have to use Full Adder.

The logic symbol of the Full adder is shown in the Fig.3. It has mainly 2 inputs which is A and B also their is third input which is CARRY IN represented by Cin and also SUM and CARRY outputs. From the Table 2 it is clear that CARRY , Cin is high when two or more than two of the ABCin are high and also when an Odd number of high ABCin inputs drives the EX-OR gates , they produces a high output and this verifies the Sum column of the truth table.

### Truth Table For Full Adder

A

B

Carry input

Sum

Carry output

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

The expressions for

* SUM S = [ (A ⊕ B) ⊕ C in]

* Carry COUT = AB +(A ⊕ B) Cin

### IV. Working Of Full Adder

Let us consider that we have to add two numbers and that are 0 and 1First. When we give the inputs A and B in which any one is high then the is Ist gate will produce output. Yhe output which is produced by it is applied to the gate number 3 and 4. But here the carry input is 0 and hence only the gate number 3 will produce output. Therefore we know that the sum of 1 and 0 is 1. Now let us consider that we give the inputs A and B and both are high i.e. 1 and 1. When A and B both are in high state then the output produced by the gate 1 is low. When the carry input is 0 then output produced by gate 3 is LOW. Therefore the output produced bu the gate 2 is applied to gate 5 and then the gate 5 produces the output carry. The sum of 1 and 1 is 10. When the input applied A and B both are 0 and the carry-input is 1only the gate 3 produces the output. The output produces by it is 1 but here is no carry output. Now we have to add a both inputs A and B and a carry input. With these conditions assume that input A is 1 and input B is 0. Therefore only the gate 1 will produce an output. When this output and the carry input is applied to 3rd and 4th gate it will produce 0 as a sum and 1 as a carry. This carry is pass from gate 4 and hence gate 5 will produce a carry output. Therefore the sum of A and carry is 10.

### V. Some special Types Of Multi Bits Adder

For example in the Fig 7 there are two numbers are given and they are 11010011 and 11101010. We cannot do the addition by of this binary number using a simple full adder because it only adds three binary numbers therefore we have to add these number using N bit adder. The addition of these number will give a output with a carry and the output produced by it is 10111101. This answer is equivalent to 189 in decimal form but we have the given inputs are 211 and 234. But it can't be possible. This is mainly happened due the reason that the carry is overflowed off the end during the additional operation. It also produced a carry output and hence the final answer which is produced by it is 445. But the Fig.7 device is only a 8 bit device and it does not produce the output more than 255 so for getting the 445 output we need to construct16bitadder.

When we are using the simple adder circuit it takes much time for the addition of binary numbers. Therefore reduction of time is also a complex task behind us . Therefore to reduce the addition computing time scientist made a carry look ahead device for addition of two or more than two binary numbers. It mainly depends upon the two things

* It mainly calculates each and every digit position whether the digit is in the right most side and producing a carry.

* It combines all these values and deduces quickly whether each group is producing a carry or not that comes in the right most side.

Let us suppose that 4 digits are chosen then carry look ahead adder function in the following way:-

* Every adder immediately calculate their result.

* Let us now suppose that in some group there is occurring of carry. Therefore at three gate delays the carry produced by the group will go to the left hand group and start propagating through the group to its left.

* If the carry produced by one group will carry on the propagation from to the left hand side then look ahead will deduce the carry. When the carry is going to left hand side the look ahead will tell the next group that a carry is coming and the next group have to receive it. It also give the information to the next group that a carry is coming.

For every bit position scientist designated two types of signals one is P and other is G depending upon the condition that a carry is only propagated from LSB. The other conditions are both the inputs given are 1 and both the inputs are 0. P is only the sum produced by the half adder and G is the carry produced by the half adder. When P and G are generated in every bit there is a generation of carry. In multi bit adding there adders designed in blocks. For the reduction of addition time these blocks are designed on the basis of propagation delay.

* Manchester carry chain

A look ahead adder is the combination of multiple carry look ahead adders and hence larger and larger adders can be created. For example in the Fig. 8 there is a 64 bit adder that mainly uses the four 16 bit CLA with two LCU.

### VI. Adder As A Compressor

The full adder can also be as a compressor. It adds the three inputs which is applied to it and gives only two binary outputs so it is also called as 3:2 compressor because it compress three inputs to only two outputs. For example when we give 101 as a input to it then it only gives 10 as output. Here the carry output is one and the sum is 0. Similarly a half adder is known as 2:2 compressors because it has only two inputs and two outputs are produced by it. The 3:2 compressor is used to speed up the addition. If the output produced by it is three binary numbers then it is called as carry save adder. If the output is more than three binary numbers then we have to design new circuits for it.

* It is used in Arithmetic logic unit (ALU)

* It is used in Floating point unit (FLU)

* Address generating devices like Cache or Memory Access Unit.

* It is used in Digital Signal Processors(DSP) architectures.

* It is used in Microprocessors.

The main limitation of the full adder is it cannot do the additions of more than three numbers. But to overcome this we are design multi bit adders but they have also the limitation of propagation delay in the circuits which we are using in the adders. When the carry is propagating then propagation delay is arising in the different gates that we are using in the circuit of adder. It affects the speed of adder. The every signal has to pass from AND gate and OR gate and that results in propagation delay. If there are four full adders present in the circuit then output has to go through 8 levels.

### IX. Subtracter

Subtracter circuits take two binary numbers as input and subtract one binary number input from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in the case of Adder). There are two types of subtracters.

* Half Subtracter.

* Full Subtracter.

### Half Subtracter

The half-subtracter is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic symbol and truth table are shown below.

### Truth Table

X

Y

D

B

0

0

0

0

0

1

1

1

1

0

1

0

1

1

0

0

Difference = X ⊕ Y

Borrow = X' Y

From the equation we can draw the half-subtracter as shown in the figure below.

### Full Subtracter

A full subtracter is a combinational circuit that performs subtraction involving three bits, namely minuend, subtrahend, and borrow-in. The logic symbol and truth table are shown below.

### Truth Table

X

Y

Bin

D

Bout

0

0

0

0

0

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

From the above table the expression for difference and the borrow for full subtractor is

D = {X'Y'Bin + X'YBin' + XY'Bin' + XYBin }

= [(X'Y' + XY)Bin] + [(X'Y + XY')Bin']

= [(X ⊕Y)'Bin] + [(X⊕Y)Bin']

= {[ X⊕ Y]⊕Bin}

Bout = {X'.Y + X'.Bin + Y.Bin}

From the above expression, we can draw the circuit below. If you look carefully, you will see that a full-subtracter circuit is more or less same as a full-adder with slight modification.

### Parallel Binary Subtracter

Parallel binary subtracter can be implemented by cascading several full-subtracters. Implementation and associated problems are those of a parallel binary adder, seen before in parallel binary adder section.Below is the block level representation of a 4-bit parallel binary subtracter, which subtracts 4-bit Y3Y2Y1Y0 from 4-bit X3X2X1X0. It has 4-bit difference output D3D2D1D0 with borrow output Bout.

### Serial Binary Subtracter

A serial subtracter can be obtained by converting the serial adder using the 2's complement system. The subtrahend is stored in the Y register and must be 2's complemented before it is added to the minuend stored in the X register.